Plan to Learn with Amy Plant at Brown Deer Middle/High School
  Plan to Learn
  • Home
  • Algebra I
    • Lesson Plans
    • Homework
    • Online Accounts >
      • Remind
      • CK-12
  • AP Physics
    • Syllabus
    • Homework
    • Labs >
      • Rotational Inertia
      • Elastic and Inelastic Collisions Lab
      • Work of Constant and Non-Constant Forces
      • Mechanical Energy
      • Speedometer Cubed Lab
      • Free Fall Lab
      • Gravity Force Lab
    • Lesson Plans
    • Discussion Corner
    • Online Accounts >
      • Edmodo
      • Khan Academy
      • Remind
    • Midterm Exam
    • AP Exam
  • Physics
    • Syllabus
    • Homework
    • Labs >
      • Momentum, Energy and Collisions
      • Mechanical Energy
      • Speedometer Cubed Lab
      • Free Fall Lab
      • Rocket Launcher
      • Newton Rides a Bike
      • Newton's 2nd Law by AP
      • Gravity Force Lab
    • Lesson Plans
    • FlipQuiz >
      • FlipQuiz 3.1
    • Online Accounts >
      • Remind
      • Edmodo
      • Khan Academy
      • Saylor Academy
  • Digital Electronics
    • Syllabus
    • Homework
    • Classwork
    • Lesson Plans
    • Discussion Corner
    • Online Accounts >
      • Edmodo
      • Khan Academy
      • Remind
    • Midterm Exam
  • Calendar
  • Contact

Classwork for Digital Electronics

Quarter 4 Classwork

cmod_s6_a_sch.pdf
File Size: 346 kb
File Type: pdf
Download File


    Activity 2.4.3 PLD Design DOB (Simulation)​

    Complete the implementation by downloading the design file to the PLD. Verify that the circuit is working as expected. If it is not, debug the design to determine your design error. Make the necessary correction and repeat steps.
    Max file size: 20MB
Submit

    Activity 2.4.1 Conclusion

    Using the Digital Logic Board (DLB), build and test your Date of Birth design. Verify that the circuit is working as designed. If it is not, do not change your design. You know that your design is good because you simulated it. If your circuit isn’t working correctly, you must have built something incorrectly. Review your circuit implementation to identify your mistakes, make the necessary corrections, and retest. Be sure to document all changes in your engineering notebook.
Submit

    Activity 2.4.1 Computational Logic DOB - Prototype

    Assigned: Monday, April 11, 2016
    Due: Thursday,April 21, 2016
    Using the Digital Logic Board (DLB), build and test your Date of Birth design. Verify that the circuit is working as designed. If it is not, do not change your design. You know that your design is good because you simulated it. If your circuit isn’t working correctly, you must have built something incorrectly. Review your circuit implementation to identify your mistakes, make the necessary corrections, and retest. Be sure to document all changes in your engineering notebook.
    Max file size: 20MB
Submit

    Activity 2.4.1 Computational Logic DOB - Simulation

    Assigned: Monday, April 11, 2016
    Due: Thursday,April 21, 2016
    Using the Circuit Design Software (CDS), enter and test your Date of Birth design. Use switches for the inputs X, Y, & Z. Verify that the circuit is working as designed. If the circuit is not working properly, review your design work and circuit implementation to identify your mistake. Make any necessary corrections and retest. Be sure to document all changes in your engineering notebook/portfolio.
    Max file size: 20MB
Submit

Quarter 3 Classwork


    Activity 2.3.5 Binary Adders: XOR and XNOR

    Assigned: Tuesday, March 22, 2016
    Due: Thursday, March 24, 2016
    Click on the title of this Activity to view a copy of this Activity as a Google Document.
    Make a copy for yourself, and when you have finished the assignment, share your copy with me.
    ​Make sure that your name appears in the file name of your copy.
    Max file size: 20MB
Submit

    Activity 2.3.3 ​Multiplexers and De-Multiplexers

    Assigned: Monday, March 14, 2016
    Due: Wednesday, March 16, 2016
    Click on the title of this Activity to view a copy of this Activity as a Google Document.
    Make a copy for yourself, and when you have finished the assignment, share your copy with me.
    ​Make sure that your name appears in the file name of your copy.
    Max file size: 20MB
Submit

    Activity 2.3.2 ​Seven Segment Display

    Assigned: Thursday, March 3, 2016
    Due: Wednesday, March 9, 2016
    Click on the title of this Activity to view a copy of this Activity as a Google Document.
    Make a copy for yourself, and when you have finished the assignment, share your copy with me.
    ​Make sure that your name appears in the file name of your copy.
    Max file size: 20MB
Submit

    Activity 2.2.5 (20 points)
    Universal Gates and K-Mapping: Fireplace Control Circuit

    Assigned: Monday, February 15, 2016
    Due: Friday, February 19, 2016
    The Acme Fireplace Company has hired you to redesign the fireplace control circuit for their latest residential gas fireplace. The fireplace burner is equipped with four thermal sensors that output a logic (1) whenever a flame is present. These sensors are connected to the fireplace control circuit which outputs a (1) to the emergency cut-off valve to keep the gas flowing (i.e., a zero will turn the gas off).
    The original design of the fireplace control circuit was quite simple. For the gas valve to remain on, all four sensors needed to output a logic (1). During field testing it was discovered that variations in gas pressure and humidity cause the thermal sensors to occasionally output a logic (0) even when a flame was present. This caused frequent unnecessary shut downs and constant customer dissatisfaction.
    Picture
    For the redesign, it has been determined that the emergency cut-off value should remain open as long as three of the four sensors indicate that a flame is present.
    Additionally, the designers have asked you to add a second output indicator to the control circuit. This indicator will output a logic (1) when the four sensors do not all agree (i.e., not all on or not all off). This indicator will be used by the service technician to diagnose whether a faulty sensor exists.

    Design (5 points)

    Design a combinational logic circuit that meets the above detailed design specifications.
    Additionally:
    • The Karnaugh mapping technique must be used to obtain the simplified logic expression for both outputs.
    • The circuit that controls the emergency cut-off valve must be implemented using only 74LS00 two-input NAND gates.
    • The circuit for the possible faulty sensor indicator must be implemented using only 74LS02 two-input NOR gates.
    Max file size: 20MB

    Simulation (5 points)

    Using the Circuit Design Software (CDS), enter and test your Fireplace Control Circuitdesign. Use switches for the inputs A, B, C, and D and a probe or LED circuit for the two outputs. Verify that the circuit is working as designed. If it is not, review your design work and circuit implementation to identify your mistake. Make any necessary corrections and retest. Be sure to document all changes in your engineering notebook/portfolio.
    Max file size: 20MB

    Prototyping (5 points)

    Using a Digital Logic Board (DLB) or Digital MiniSystem (DMS), build and test your Fireplace Control Circuit design. Verify that the circuit is working as designed. If it is not, YOU SHOULD NOT CHANGE YOUR DESIGN. You know that your design functions because you simulated it. If your circuit isn’t working correctly, you must have built something incorrectly. Review your circuit implementation to identify your mistakes, make the necessary corrections, and retest. Be sure to document all changes in your engineering notebook/portfolio.

    Conclusion (5 points)

    Using your engineering notebook/portfolio as a guide, write a conclusion (minimum 250 words) on your website that describes the process that you used to design, simulate, and build your Fireplace Control Circuit. This conclusion must include all of your design work (i.e., truth table, K-Maps, etc.), preliminary and final schematics, parts list, and a digital photograph of your final circuit. The documentation should be complete enough that a student with a similar knowledge of digital electronics could reproduce your design without any additional assistance.
Submit

    Activity 2.2.4 Design Tool: Logic Converter

    Assigned: Thursday, February 11, 2016
    Due: Monday, February 15, 2016
    Now that you are all experts at logic simplification using Boolean algebra and K-Mapping and can implement virtually any combinational design using AOI, NAND, and NOR gates, it’s time to let you in on a little secret. A tool located within the Multisim Circuit Design Software, called the Logic Converter, can do much of this work for you. You might be asking yourself why you weren’t given this tool sooner.  As an engineer you need to know how to design these types of circuits with and without the aid of such tools. Besides, who do you think designs tools like the Logic Converter? That’s right, an engineer.
    In this activity you will complete a brief tutorial and use the Logic Converter to create and simulate both an AOI and NAND circuit design.

    Use the Logic Converter to create an AOI and NAND only logic circuit for the Majority Vote Project.

    1. Enter the truth table for the Majority Vote – Voting Machine into the Logic Converter. Unfortunately, you can’t change the variable names in the Logic Converter, so variables P, V, S, and T will be represented by A, B, C, and D.
    2. Use the Logic Converter to first generate, and then simplify the logic expression for the output Vote.
    3. Use the Logic Converter to create the AOI logic implementation of the Majority Vote – Voting Machine. Use switches for the inputs A, B, C, and D (which you should now rename P, V, S, and T)and a probe or LED circuit for the output Vote. Verify that the circuit is working as expected.  Save a copy and upload.
    4. Use the Logic Converter to create the NAND only logic implementation of the Majority Vote – Voting Machine. Use switches for the inputs A, B, C, and D (again, you should rename them P, V, S, and T)and a probe or LED circuit for the output Vote. Verify that the circuit is working as expected. Save a copy and upload.

    Conclusion


    Max file size: 20MB
    Max file size: 20MB
Submit

    Activity 2.2.3 Universal Gates: NOR Only

    Assigned: Tuesday, February 9, 2016
    Due: Thursday, February 11, 2016
    In this activity you will implement NOR only combinational logic circuits for the two outputs Booth and Alarm. 
    1. In your weekly notebooks,  re-draw the AOI circuits that you designed in Activity 2.2.2 NAND Logic Design.
    2. Re-implement these circuits assuming that only 2-input NOR gates (74LS02) are available. Draw these circuits in your notebook.
    3. Using the CDS, enter and test the two logic circuits that you designed. Use switches for the inputs A, B, C, and D and a probe or LED circuit for the outputs Booth and Alarm. Verify that the circuits are working as expected.  Print a copy of the circuit and attach it to your notebook.
      Note: Even though the two circuits work independently, they are part of one design and should be simulated, tested, and prototyped together.
    4. Using the DLB, build and test the NOR logic circuits that you designed and simulated. Verify that the circuits are working as expected and that the results match the results of the simulation.  ​

    Conclusion


    Max file size: 20MB
Submit

    Activity 2.2.2 Universal Gates: NAND Only

    Assigned: Wednesday, February 3, 2016
    Due: Friday, February 5, 2016
    The block diagram shown below represents a voting booth monitoring system. For privacy reasons, a voting booth can only be used if the booth on either side is unoccupied. The monitoring system has four inputs and two outputs. Whenever a voting booth is occupied, the corresponding input (A, B, C, & D) is a (1). The first output, Booth, is a (1) whenever a voting booth is available. The second output, Alarm, is a (1) whenever the privacy rule is violated.
    Voting Booth
    In this activity you will implement NAND only combinational logic circuits for the two outputs Booth and Alarm. These NAND only designs will be compared with the original AOI implementations in terms of efficiency and gate/IC utilization. In a future activity, these NAND only designs will be compared to the circuits implemented using only NOR gates.
    1. In your weekly notebooks, draw the AOI circuits that implement the simplified logic expressions Booth and Alarm. Limit this implementation to only 2-input AND gates (74LS08), 2-input OR gates (74LS32), and inverters (74LS04).
    2. Re-implement these circuits assuming that only 2-input NAND gates (74LS00) are available. Draw these circuits in your notebook.
    3. Using the CDS, enter and test the two logic circuits that you designed. Use switches for the inputs A, B, C, and D and a probe or LED circuit for the outputs Booth and Alarm. Verify that the circuits are working as expected. 
      Note: Even though the two circuits work independently, they are part of one design and should be simulated, tested, and prototyped together.
    4. Using the DLB, build and test the NAND logic circuits that you designed and simulated. Verify that the circuits are working as expected and the results match the results of the simulation. 
    Max file size: 20MB
Submit

Quarter 2 Classwork


Activity 2.1.3 Activity 2.1.3 AOI Logic Implementation (Breadboard)

Assigned: Thursday, January 7, 2016
Due: Tuesday, January 19, 2016

Multimeter Activity

Assigned: Thursday, December 18, 2015
For those students who are not attending the field trip, read the following two articles
  • ABCs of multimeter safety
  •  How to Use a Multimeter
Take notes in your notebook, as I will check them when we return.
​
There will be a quiz on Monday for all students about the appropriate use of a multimeter.

Activity 1.2.4 Introduction to Sequential Logic Design: Counters (DLB)

Assigned: Monday, November 16, 2015
Due: Friday, November 20, 2015
1.2.4.a_sequentiallogicdesign_counters_dlb.docx
File Size: 472 kb
File Type: docx
Download File

NI Digital Electronics FPGA Board
File Size: 1480 kb
File Type: pdf
Download File

Picture
Submit Activity 1.2.4

Quarter 1 Homework


    Activity 1.1.6 Component Identification

    Assigned: Monday, October 19, 2015
    Due: Wednesday, October 21, 2015
    View the assignment via the PLTW web-site
    Download the assignment as a document: 1.1.6.A ComponentIdentification Digital.docx

    Problems 1 - 6

    Max file size: 20MB
    Discuss things like ... what was new to you, what was easy, what you found difficult, etc ...
Submit

    Activity 1.1.5c Circuit Theory: Breadboarding

    Assigned: Monday, October 12, 2015
    Due: Wednesday, October 15, 2015
    View the assignment via the PLTW web-site
    Download the assignment as a document: 1.1.5.Ac CircuitTheoryBreadboard.docx

    Max file size: 20MB
    Max file size: 20MB

    [object Object]
    Max file size: 20MB
    Max file size: 20MB

    Conclusion

    Discuss things like ... what was new to you, what was easy, what you found difficult, etc ...
Submit

    Activity 1.1.5b Circuit Theory: Simulations

    Assigned: Thursday, October 8, 2015
    Due: Monday, October 13, 2015
    View the assignment via the PLTW web-site
    Download the assignment as a document: 1.1.5.Ab CircuitTheorySimulation.docx



    [object Object]
    [object Object]

    Conclusion
    [object Object]

    Discuss things like ... what was new to you, what was easy, what you found difficult, etc ...
Submit

    Activity 1.1.4 Component Identification: Analog

    Assigned: Monday, September 28, 2015
    Due: Wednesday, September 30, 2015
    View the presentation we went over in class: 1.1.4 ComponentIdentificationAnalog.pptx
    View the assignment via the PLTW web-site
    Download the presentation as a document: 1.1.4.A ComponentIdentificationAnalog.docx
    You may either print the document and turn it into me, or download the Microsoft© Word Document and submit it to me electronically.
    Max file size: 20MB
    Discuss things like ... what was new to you, what was easy, what you found difficult, etc ...
Submit

    Activity 1.1.2 Investigating Basic Circuits (DLB)

    Assigned: Thursday, September 17, 2015
    Due: Monday, September 21, 2015
    View the presentation we went over in class: 1.1.2a PreInvestigating Basic Circuits.pptx
    View the assignment via the PLTW web-site
    Download the presentation as a document: 1.1.2.A Investigating Basic Circuits_DLB.docx
    You may either print the document and turn it into me, or download the Microsoft© Word Document and submit it to me electronically.
    Max file size: 20MB
    Discuss things like ... what was new to you, what was easy, what you found difficult, etc ...
Submit

    CW 1.3 Getting Started with Multisim®: Combinational Logic

    Assigned: Tuesday, September 15, 2015
    Due: Thursday, September 17, 2015
    Watch the Multisim®: Combinatioanl Logic
    The estimated time to complete this assignment is 45 minutes. This time may vary per user.
    Max file size: 20MB
    Tell me what you thought about these questions (use complete sentences).
Submit

    CW 1.2 Getting Started with Multisim®: Sequential Logic

    Assigned: Friday, September 11, 2015
    Due: Tuesday, September 15, 2015
    Watch the Multisim®: Sequential Logic
    The estimated time to complete this assignment is 45 minutes. This time may vary per user.
    Max file size: 20MB
    Tell me what you thought about these questions (use complete sentences).
Submit

    CW 1.1 Getting Started with Multisim®: Analog Circuits

    Assigned: Wednesday, September 9, 20015
    Due: Friday, September 11, 2015
    Max file size: 20MB
    Watch the Multisim®: Analog Circuits
    The estimated time to complete this assignment is 60 minutes. This time may vary per user.
    Tell me what you thought about these questions (use complete sentences).
Submit
Plant to Learn • Copyright © 2015